Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum

OBJECTIVES
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VHDL Library
VLSI Libraries
Course Modules
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The goal of this project is to improve educational practices and student learning through development of materials that provide for easy integration of asynchronous concepts into existing course structures. No readily available educational materials currently exist for this topic. Following are the project's specific objectives:

  • Develop lecture notes, example problems, and group projects to introduce asynchronous paradigms,
  • Develop a static VHDL library of fundamental asynchronous gates and components,
  • Develop a static transistor-level library of fundamental asynchronous gates,
  • Develop a static physical-level library of fundamental asynchronous gates,
  • Develop a Design-For-Test (DFT) library of fundamental asynchronous gates,
  • Integrate the developed materials into two Undergraduate/Graduate-level UMR courses: Digital System Modeling with VHDL and Introduction to VLSI,
  • Have the developed materials reviewed externally, and

  • Disseminate the developed materials to faculty members at other institutions.

The developed materials will integrate cutting-edge technology into standard educational practices, to provide a low-cost, innovative addition to the Computer Engineering curriculum. The design modules focus on the delay-insensitive NULL Convention Logic (NCL) paradigm.