About My Work

Research Interests

  • Asynchronous Logic
  • NULL Convention Logic (NCL)
  • CAD Tool Development for Asynchronous Circuits
  • Asynchronous FPGA Design
  • VHDL
  • VLSI
  • Computer Architecture
  • Embedded System Design
  • Evolvable Hardware
  • Secure/Trustable Hardware
  • Wireless Sensor Networks

Book

Scott C. Smith and Jia Di, Designing Asynchronous Circuits using NULL Convention Logic (NCL), Synthesis Lectures on Digital Circuits and Systems, Vol. 4/1, July 2009, Morgan & Claypool Publishers (doi: 10.2200/S00202ED1V01Y200907DCS023).

Dissertation

S. C. Smith, "Gate and Throughput Optimizations for NULL Convention Self-Timed Digital Circuits," Ph.D. Dissertation, School of Electrical Engineering and Computer Science, University of Central Florida, May 2001.

Courses Taught

  • ELEG 5914 / ELEG 4914 / CSCE 4914 - Advanced Digital Design - SP12, Sp11, Sp10
  • ELEG 2904 - Digital Design - FS11
  • ELEG 2904 / CSCE 2114 - Digital Design - FS10, FS09
  • ELEG 2913 / CENG 2123 - Digital Design II - Sp09, Sp08
  • ELEG 2903 / CENG 2113 - Digital Design I - FS08, FS07
  • CpE 412 - Digital Logic (@ University of Missouri - Rolla) - FS06, FS05, FS04, FS03, FS02
  • CpE 318 - Digital System Modeling (@ University of Missouri - Rolla) - WS07, WS06, WS05, WS04, WS03, WS02
  • CpE 111 - Introduction to Computer Engineering (@ University of Missouri - Rolla) - FS06, FS05, FS01
  • EEL 5708 - High Performance Computer Architecture (@ University of Central Florida) - FS99

Journal Publications

  1. S. C. Smith, W. K. Al-Assadi, and J. Di, "Integrating Asynchronous Digital Design into the Computer Engineering Curriculum," IEEE Transactions on Education, Vol. 53/3, pp. 349-357, August 2010.
  2. A. Bailey, A. Al Zahrani, G. Fu, J. Di, and S. C. Smith, "Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power,” Journal of Low Power Electronics, Vol. 4/3, pp. 337-348, December 2008.
  3. V. Satagopan, B. Bhaskaran, A. Singh, and S. C. Smith, "Energy Calculation and Estimation for Delay-Insensitive Digital Circuits," Elsevier’s Microelectronics Journal, Vol. 38/10-11, pp. 1095-1107, October/November 2007.
  4. V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, S. C. Smith, and S. Kakarla, "DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits," IEEE Transactions on VLSI Systems: Special Issue on System on Chip Integration, Vol. 15/10, pp. 1155-1159, October 2007.
  5. S. C. Smith, "Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits," IEEE Transactions on VLSI Systems, Vol. 15/6, June 2007.
  6. G. K. Venayagamoorthy, S. C. Smith, and G. Singhal, "Particle Swarm Based Optimal Partitioning Algorithm for Combinational CMOS Circuits," Elsevier’s Engineering Applications of Artificial Intelligence, Vol. 20/2, pp. 177-184, March 2007.
  7. S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," Elsevier's Microelectronic Engineering Journal: Special Issue on VLSI Design and Test, Vol. 84/2, pp. 280-287, February 2007.
  8. S. C. Smith, "Speedup of NULL Convention Digital Circuits Using NULL Cycle Reduction," Elsevier's Journal of Systems Architecture, Vol. 52/7, pp. 411-422, July 2006.
  9. S. C. Smith, "Development of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit," Elsevier's Integration, The VLSI Journal, Vol. 39/1, pp. 12-28, September 2005.
  10. S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, "Optimization of NULL Convention Self-Timed Circuits," Elsevier's Integration, The VLSI Journal, Vol. 37/3, pp. 135-165, August 2004.
  11. S. K. Bandapati, S. C. Smith, and M. Choi, "Design and Characterization of NULL Convention Self-Timed Multipliers," IEEE Design and Test of Computers: Special Issue on Clockless VLSI Design, Vol. 30/6, pp. 26-36, November-December 2003. Figures
  12. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "NULL Convention Multiply and Accumulate Unit with Conditional Rounding, Scaling, and Saturation," Elsevier's Journal of Systems Architecture, Vol. 47/12, pp. 977-998, June 2002.
  13. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "Delay-Insensitive Gate-Level Pipelining," Elsevier's Integration, the VLSI Journal, Vol. 30/2, pp. 103-131, October 2001.

Conference Publications

  1. L. Zhou, M. Huang, and S. C. Smith, "High-Performance and Area-Efficient Hardware Design for Radix-2k Montgomery Multipliers," International Conference on Computer Design, pp. 65-71, July 2011.
  2. W. Collins, D. Sanchez, Z. Sharp, S. C. Smith, and J. Wu, "Developing a Remote Digital Wildlife Camera Triggered by Spatially Deployed Infrared Sensors," International Conference on Embedded Systems and Applications, pp. 21-28, July 2011.
  3. P. Killeen, J. Monkus, E. Klessig, D. Hearn, J. Wu, and S. C. Smith, "Developing a Smart Home System," International Conference on Embedded Systems and Applications, pp. 148-152, July 2011.
  4. L. Zhou and S. C. Smith, "Standby Power Reduction Techniques for Asynchronous Circuits with Indeterminate Standby States," International Conference on Computer Design, pp. 10-16, July 2011.
  5. B. Hollosi, J. Di, S. C. Smith, and H. A. Mantooth, "Delay-Insensitive Asynchronous Circuits for Operating under Extreme Temperatures," Government Microcircuit Applications & Critical Technology Conference, pp. 407-410, March 2011.
  6. S. C. Smith and J. Di, "Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum Throughout the Nation," NSF CCLI/ TUES PI Conference, January 2011.
  7. L. Zhou and S. C. Smith, "Static Implementation of Quasi-Delay-Insensitive Pre-Charge Half-Buffers," IEEE Midwest Symposium on Circuits and Systems, pp. 636-639, August 2010. (nominated for best student paper)
  8. L. Zhou, S. C. Smith, and J. Di, "Bit-Wise MTNCL: An Ultra-Low Power Bit-Wise Pipelined Asynchronous Circuit Design Methodology," IEEE Midwest Symposium on Circuits and Systems, pp. 217-220, August 2010.
  9. S. Yancey and S. C. Smith, "A Differential Design for C-Elements and NCL Gates," IEEE Midwest Symposium on Circuits and Systems, pp. 632-635, August 2010. (nominated for best student paper)
  10. S. C. Smith, D. Roclin, and J. Di, "Delay-Insensitive Cell Matrix," International Conference on Computer Design, pp. 67-73, July 2010.
  11. C. M. Smith and S. C. Smith, "Comparison of NULL Convention Booth2 Multipliers," International Conference on Computer Design, pp. 3-9, July 2010.
  12. W. A. Cilio, M. J. Linder, C. Porter, J. Di, and S. C. Smith, "Side-Channel Attack Mitigation Using Dual-Spacer Dual-Rail Delay-Insensitive Logic (D3L),” IEEE SoutheastCon, March 2010.
  13. B. Hollosi, T. Zhang, R. S. P. Nair, Y. Xie, J. Di, and S. C. Smith, "Investigation and Comparison of Thermal Distribution in Synchronous and Asynchronous 3D ICs," IEEE International Conference on 3D System Integration, September 2009.
  14. J. Wu and S. C. Smith, "Integrated Software-Hardware Design for Ultra-Low Power Infrastructure Monitoring," IEEE Intelligent Transportation Systems Conference, pp. 375-382, October 2009.
  15. L. Zhou and S. C. Smith, “Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit,” IEEE Midwest Symposium on Circuits and Systems, pp. 499-502, August 2009.
  16. R. S. P. Nair, S. C. Smith, and J. Di, “Delay-Insensitive Ternary Logic," International Conference on Computer Design, pp. 3-9, July 2009.
  17. P. Palangpour, G. K. Venayagamoorthy, and S. C. Smith, “Particle Swarm Optimization: A Hardware Implementation," International Conference on Computer Design, pp. 134-139, July 2009.
  18. A. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, "Ultra-Low Power Delay-Insensitive Circuit Design,” IEEE Midwest Symposium on Circuits and Systems, August 2008.
  19. B. Hollosi, M. Barlow, G. Fu, C. Lee, J. Di, S. C. Smith, H. A. Mantooth, and M. Schupbach, "Delay-Insensitive Asynchronous ALU for Cryogenic Temperature Environments,” IEEE Midwest Symposium on Circuits and Systems, August 2008.
  20. S. C. Smith, W. K. Al-Assadi, and J. Di, “Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum Throughout the Nation,” NSF CCLI PI Conference, August 2008.
  21. I. P. Dugganapally, W. K. Al-Assadi, V. Pillai, and S. C. Smith, "Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Semi-Static NCL Circuits,” IEEE Region 5 Technical Conference, April 2008.
  22. I. P. Dugganapally, W. K. Al-Assadi, T. Tammina, and S. C. Smith, "Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL,” IEEE Region 5 Technical Conference, April 2008.
  23. S. C. Smith and W. K. Al-Assadi, "Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum," 6th ASEE Global Colloquium on Engineering Education, October 2007.
  24. S. C. Smith and W. K. Al-Assadi, "Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum," The 2007 ASEE Annual Conference & Exposition, June 2007.
  25. S. C. Smith, "Design of a Logic Element for Implementing an Asynchronous FPGA," 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 13-22, February 2007.
  26. S. C. Smith and W. K. Al-Assadi, "Teaching Asynchronous Digital Design in the Undergraduate Computer Engineering Curriculum," IEEE Region 5 Technical Conference, April 2007.
  27. M. V. Joshi, S. Gosavi, V. Jagadeesan, A. Basu, S. Jaiswal, W. K. Al-Assadi, and S. C. Smith, "NCL Implementation of Dual-Rail 2s Complement 8×8 Booth2 Multiplier using Static and Semi-Static Primitives," IEEE Region 5 Technical Conference, April 2007.
  28. S. R. Mallepalli, S. Kakarla, S. Burugapalli, S. Beerla, S. Kotla, P. K. Sunkara, W. K. Al-Assadi, and S. C Smith, "Implementation of Static and Semi-Static Versions of a Quad-Rail NCL 24+8x8 Multiply and Accumulate Unit," IEEE Region 5 Technical Conference, April 2007.
  29. R. S. P. Nair, F. Kacani, R. Bonam, S. M. Gandla, S. K. Chitneni, V. Kadiyala, W. K. Al-Assadi, and S. C. Smith, "Implementation of Static and Semi-Static Versions of a Bit-Wise Pipelined Dual-Rail NCL 2s Complement Multiplier," IEEE Region 5 Technical Conference, April 2007.
  30. S. C. Smith and J. Di, "Detecting Malicious Logic Through Structural Checking," IEEE Region 5 Technical Conference, April 2007.
  31. J. Di and S. C. Smith, "A Hardware Threat Modeling Concept for Trustable Integrated Circuits," IEEE Region 5 Technical Conference, April 2007.
  32. V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, S. C. Smith, and S. Kakarla, "Design for Test Techniques for Asynchronous NULL Conventional Logic (NCL) Circuits," International Joint Conference on Computer, Information, and Systems Sciences, and Engineering, December, 2006.
  33. S. C. Smith, "Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum," The 2006 ASEE Midwest Section Annual Conference, September 2006.
  34. V. Satagopan, B. Bhaskaran, W. Al-Assadi, and S. C. Smith, "Automation in Design for Test for Asynchronous Null Conventional Logic (NCL) Circuits," 12th NASA Symposium on VLSI Design, October, 2005.
  35. S. C. Smith, "Group Selection in a Senior/Graduate Level Digital Circuit Design Course," The 2005 ASEE Midwest Section Annual Conference, September 2005.
  36. B. Bhaskaran, V. Satagopan, and S. C. Smith, "High-Speed Energy Estimation for Delay-Insensitive Circuits," The 2005 International Conference on Computer Design, pp. 35-41, June 2005.
  37. A. Singh and S. C. Smith, "Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation," The 2005 International Conference on Computer Design, pp. 115-121, June 2005.
  38. B. Bhaskaran, V. Satagopan, W. Al-Assadi, and S. C. Smith, "Implementation of Design For Test for Asynchronous NCL Designs," The 2005 International Conference on Computer Design, pp. 78-84, June 2005.
  39. G. Singhal, G. K. Venyagamoorthy, and S. C. Smith, "An Optimal Partitioning Algorithm for Combinational CMOS Circuits Using Particle Swarm Optimization," 14th IEEE North Atlantic Test Workshop, pp. 87-92, May 2005.
  40. S. C. Smith, "Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput," The 2004 International Conference on VLSI, pp. 407-412, June 2004.
  41. S. C. Smith, "Design of a NULL Convention Self-Timed Divider," The 2004 International Conference on VLSI, pp. 447-453, June 2004.
  42. S. C. Smith, "Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-wise Completion Strategy," The 2003 International Conference on VLSI, pp. 143-149, June 2003.
  43. S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," The 2003 International Conference on VLSI, pp. 178-184, June 2003.
  44. S. C. Smith, "Speedup of Self-Timed Digital Systems Using Early Completion," The IEEE Computer Society Annual Symposium on VLSI, pp. 107-113, April 2002.
  45. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction," The 10th International Workshop on Logic and Synthesis, pp. 185-189, June 2001.
  46. S. C. Smith and M. J. Devaney, "Fourier Based Three Phase Power Metering System," The 17th IEEE Instrumentation and Measurement Technology Conference, Vol. 1, pp. 30-35, May 2000.

Patents

  1. Jia Di and Scott Christopher Smith, Ultra-Low Power Multi-Threshold Asynchronous Circuit Design, U.S. Patent: 7,977,972 B2, July 12, 2011.
  2. Robert Nathan Nelms and Scott Christopher Smith, Selective Call Message Formatting, U.S. Patent: 6,148,178 November 14, 2000; International Patent: WO9838609 September 3, 1998.
  3. Frederick Loring Kampe, Scott Christopher Smith, Jheroen Pieter Dorenbosch, and Robert Nathan Nelms, Reliably Updating an Information Service Message, U.S. Patent: 6,016,107 January 18, 2000; International Patent: WO9839930 September 11, 1998.
  4. Robert Nathan Nelms, Marcus A. Gade, Michael J. DeLuca, Frederick Loring Kampe, and Scott Christopher Smith, Selective Call Device and Method for Battery Saving During Information Services, U.S. Patent: 5,929,773 July 27, 1999; International Patent: WO9838809 September 3, 1998.
  5. Scott Christopher Smith, Frederick Loring Kampe, and Jheroen Pieter Dorenbosch, Insert/Delete Modification of Information Service Message, International Patent: WO9913658 March 18, 1999.
  6. Robert Nathan Nelms, Tom Klein, Scott Christopher Smith, and Frederick Loring Kampe, Performing Updates to Multiple Information Service Topics Using a Single Command, International Patent: WO9839929 September 11, 1998.

Grants

Total: $3,272,570; Total as PI: $1,641,218 (50%); Total Share: $1,261,493 (39%)

  1. M. Thornton (34% from SMU), B. Reese (33% from MSU), and S. C. Smith (33%), "SHF: Small: A Register Transfer Level Toolset for Low Power Asynchronous Design Using Null Convention Logic," NSF CCF-1116405, $350,000, July 2011 - June 2013.
  2. J. Di (50%) and S. C. Smith (50%), "Development of an Ultra-Low Power IC Design and Packaging to Provide a Variety of Critical Anti-Tamper Safeguards," Air Force SBIR Phase I subcontract through Space Photonics, Inc., $33,303, January 2011 - September 2011.
  3. J. Di (50%) and S. C. Smith (50%), "Low-Power Radiation-Hardened Delay-Insensitive Asynchronous Microcontroller Technology Capable of Operating in Extreme Temperature Environments," NASA SBIR Phase I subcontract through APEI, Inc., $33,303, January 2011 - June 2011.
  4. J. Di (50%), S. C. Smith (40%), and H. A. Mantooth (10%), "Ultra-Low Power Delay-Insensitive Asynchronous Circuits," SRC, $294,000, March 2011 - February 2014.
  5. S. C. Smith (50%) and J. Wu (50%), "REU Site: Summer Research Experiences in Wireless Sensor Networks - Design and Applications," NSF, EEC-1005106, $367,734, May 2010 - April 2013.
  6. S. C. Smith, "Lunar Regolith Excavator Team Proposal," NASA, $4,000, October 2010 - June 2011.
  7. S. C. Smith (20%), Po-Hao Huang (20%), Uche Wejinya (20%), H. Alan Mantooth (20%), and Larry Roe (20%), "Lunar Regolith Excavator Team Proposal," NASA, $5,000, October 2009 - May 2010.
  8. S. C. Smith (25%), J. Di (25%), J. Wu (25%), and H. A. Mantooth (25%), “GAANN: Asynchronous and Mixed-Signal IC Design and CAD for Next Generation Ultra-Low Power Computing and Communication Systems for Medical, Mobile, and Sensor Network Applications,” U.S. Department of Education, P200A090279, $514,512 ($102,903 UA matching), August 2009 – August 2012.
  9. J. Di (34%), S. C. Smith (33%), and H. Zhou (33%), “TC: Medium: Collaborative Research: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer Protection,” NSF, CNS-0904943 and CNS-0905223, $200,000, September 2009 – August 2011.
  10. J. Wu (50%) and S. C. Smith (50%), “Development of Ultra-Low Power Smart Biomedical Sensors: an Integrated Software-Hardware Approach,” Arkansas Biosciences Institute, $42,900, July 2009 – June 2010.
  11. J. Di (50%), S. C. Smith (40%), and J. P. Parkerson (10%), “SEU/SEL Resistant Ultra-Low Power Asynchronous Processor Design for Low-Temperature Applications,” NASA SBIR Phase I through Space Photonics, Inc., $33,317, February 2009 – July 2009.
  12. J. Di (50%), S. C. Smith (35%), and H. A. Mantooth (15%), "DIMLOG: Ultra-Low Power Delay-Insensitive Asynchronous Circuits," DARPA, $305,326, October 2008 - March 2010.
  13. S. C. Smith (25%) and B. Driskill (75%), “Automated Bit-Wise Completion for Asynchronous NULL Convention Digital Circuits,” University of Arkansas Student Undergraduate Research Fellowship (SURF) grant, $3,900, January 2008 – October 2008.
  14. S. C. Smith (50%), J. Di (25%), and W. K. Al-Assadi (25%), “Collaborative Research: Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum throughout the Nation,” NSF CCLI Phase II, DUE-0717572 and DUE-0717767, $499,999, August 2007 – July 2011.
  15. G. K. Venayagamoorthy (65%), S. C. Smith (20%), and K. A. Corzine (15%), “GAANN: Advanced Computational Techniques and Real-Time Simulation Studies for the Next Generation Energy Systems,” Department of Education, P200A070504, $360,000, June 2007 – May 2010.
  16. S. C. Smith (67%) and W. K. Al-Assadi (33%), “Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum,” NSF CCLI Phase 1, DUE-0536343, $94,789, February 15, 2006 – June 30, 2007.
  17. K. Krishnamurthy (50%) and S. C. Smith (50%), “REU: Summer Research Experiences for Undergraduates in Micro Mechatronic Systems,” NSF, EEC-0139117, $94,214, March 1, 2006 - February 28, 2007.
  18. S. C. Smith, “Group Selection in a Senior/Graduate Level Digital Circuit Design Course,” University of Missouri New Faculty Teaching Scholars, $686, April 1, 2005 – September 16, 2005.
  19. S. C. Smith, “DSP Filtering for Wayside MUX,” Quackenbush Engineering Solutions & Technologies, LLC., $6,800, July 16, 2004 – October 15, 2004.
  20. S. C. Smith, “Evaluation of a Dissolution Rate Monitor on Base-soluble Polymers,” Brewer Science, Inc., $3,731, September 2003 – December 2003.
  21. S. C. Smith, “Development and Speedup of Self-Timed Digital Circuits,” University of Missouri Research Board, $23,400, January 2002 – May 2003.

Ph.D. Dissertations Advised

  1. Venkat Satagopan, “Automated Pipelining Optimization, Energy Estimation, and DFT Techniques for Asynchronous NULL Convention Circuits using Industry-Standard CAD Tools,” Department of Electrical & Computer Engineering, University of Missouri – Rolla, May 2007.
  2. Bonita Bhaskaran, “Automated Synthesis and NCR Optimization for Asynchronous NULL Convention Circuits using Industry-Standard CAD Tools,” Department of Electrical & Computer Engineering, University of Missouri – Rolla, May 2007.

Master's Theses Advised

  1. Satish Bandapati, "Design and Characterization of Asynchronous Delay-Insensitive Arithmetic Components Using Null Convention Logic," Department of Electrical & Computer Engineering, University of Missouri – Rolla, May 2003.
  2. Sareen Devireddy, "Schematic Capture Design & Power Calculation for NULL Convention Delay-Insensitive Digital Circuits using Mentor Graphics Design Tool Suite," Department of Electrical & Computer Engineering, University of Missouri – Rolla, June 2003.
  3. Sasikanth Duggini, "Design Tools for NULL Convention Logic Circuits," Department of Electrical & Computer Engineering, University of Missouri - Rolla, May 2004.
  4. Hiten Dharavat, "Radiation Testing of COTC CMOS Chips Against Continuous Gamma Radiations," Department of Electrical & Computer Engineering, University of Missouri – Rolla, May 2004 (co-advised with Dr. Akira Tokuhiro in Nuclear Engineering).
  5. Anshul Singh, "Using a VHDL Testbench for Transistor-Level Simulation and Power Calculation of NULL Convention Asynchronous Digital Circuits," Department of Electrical & Computer Engineering, University of Missouri – Rolla, December 2004.
  6. Arun Balasubramanian, "An Asynchronous FPGA for NULL Convention Logic Circuits," Department of Electrical & Computer Engineering, University of Missouri – Rolla, January 2005.
  7. Ibrahim Kubilay, “3D Modeling of String Motion,” Department of Electrical & Computer Engineering, University of Missouri – Rolla, May 2006.
  8. Ravi Sankar Parameswaran Nair, “Delay-Insensitive Ternary Logic (DITL),” Department of Electrical & Computer Engineering, University of Missouri – Rolla, August 2007.
  9. Samarsen Mallepalli, “Generic Algorithms and NULL Convention Logic Hardware Implementation for Unsigned and Signed Quad-Rail Multiplication,” Department of Electrical & Computer Engineering, University of Missouri – Rolla, August 2007.
  10. Zhen Song, "Implementation of Fast Fourier Transform Processor in NULL Convention Logic," University of Arkansas, May 2011.

Undergraduate Projects Advised

  1. Sarah Rosenbaum, Jim Ballmann, Nick Hamilton, and Alexis Sietins, “Stealth Cam Communications,” Senior Design Project, University of Missouri – Rolla, December 2005.
  2. Robert Pangrazio, Eric Peters, and Brad Roberts, “Human Interface Device - MOKI,” Senior Design Project, University of Missouri – Rolla, December 2005.
  3. Jonathan Baldwin, Etenia Ponder, and Lindsay Waters, “Autonomous Stair-Climbing Wheelchair,” REU Project, University of Missouri – Rolla, Summer 2006.
  4. José Martí, Raj Mishra, and Katrina Stevens, “Developing a Fishing System for Tetraplegics,” REU Project, University of Missouri – Rolla, Summer 2006.
  5. Warren Brooks, Steven Ortiz, Adam Kuentzler, and Nicholas Grither, “Fishing System for Tetraplegics,” Senior Design Project, University of Missouri – Rolla, December 2007.
  6. Jessica Rutledge, "Biomagnetic Imaging with the Selective Minimum Norm Method," REU Project, University of Arkansas, Summer 2008 (co-advised with Dr. Magda El-Shenawee).
  7. Chris Bridges and Faheem Ibrahim, "Dynamic Power Control and Optimization of Autonomous Stair-Climbing Wheelchair," Senior Design Project, University of Arkansas, to be completed December 2008.
  8. Chris Farnell and Michael Helms, "Multistage Gauss Gun with Dual Axis Tracking," Senior Design Project, University of Arkansas, May 2010.
  9. Brian Stalling, Jacob Williams, Justin Robertson, and Shannen Adcock, "Lunar Regolith Excavator Communications System," Senior Design Project, University of Arkansas, May 2010.
  10. Son Ha, Nadia Smith, and Adeline Kamaha, "Lunar Regolith Excavator Control System," Senior Design Project, University of Arkansas, May 2010.
  11. Zihao Gong, "Design Project to Showcase Advantages of Asynchronous vs. Synchronous Circuits," Senior Honors Project, August 2010.
  12. William Collins, Daniel Sanchez, and Zachary Sharp, "Developing a Remote Digital Wildlife Camera Triggered by Spatially Deployed Infrared Sensors," REU Project, University of Arkansas, Summer 2010 (co-advised with Dr. Jingxian Wu).
  13. Peter Killeen, John Monkus, Biz Klessig, and D. Hearn, "Smart Home Monitoring System," REU Project, University of Arkansas, Summer 2010 (co-advised with Dr. Jingxian Wu).
  14. Matthew Bell and Tavis Clemmer, "Autonomous Stair-Climbing Wheelchair Improvements," Senior Design Project, University of Arkansas, December 2010.
  15. Matthew Huffmaster, Brett Sparkman, Christina Smith, David Fryauf, Alex Arguelles, and Nicholas Chiolino, "NASA Lunabotics Competition," Senior Design Project, May 2011.
  16. Biz Klessig, Hanna Jones, and Kurt Waldrup, "IEEE Robotics Competition," Senior Design Project, May 2011.
  17. Brett Sparkman, "Utilizing NULL Cycle Reduction for Decreasing Energy Usage," Honors Research Project, May 2011.
  18. Justin Roark, "Demonstrating the Advantages of Asynchronous Circuits using an 8051 Microcontroller," Honors Research Project, May 2011.
  19. Matthew Huffmaster, "Porting the NCL NULL Cycle Reduction Tool from Mentor to Synopsys," Independent Study Project, May 2011.
  20. Hanna Jones, "Porting the NCL Threshold Combinational Reduction Tool from Mentor to Synopsys," Independent Study Project, May 2011.
  21. Alex Arguelles, "Porting the NCL Gate Level Pipelining Tool from Mentor to Synopsys," Independent Study Project, May 2011.
  22. John Amos, Arturo Chavez, Justen Dawson, and Trent Chudej, "Unexploded Ordnances (UXO) Detection with Cooperative and Mobile Robots," REU Project, University of Arkansas, Summer 2011 (co-advised with Dr. Jingxian Wu).
  23. Mario McGregor, Chris Briley, Theresa Akede, and Ashley Jackson, "Developing an Ultra-Low Power Remote Infrastructure Monitoring System," REU Project, University of Arkansas, Summer 2011 (co-advised with Dr. Jingxian Wu).
  24. Joe Post, Alyssa Baccus, and Dylan Underwood, "Developing a Remote Fish Monitoring System," REU Project, University of Arkansas, Summer 2011 (co-advised with Dr. Jingxian Wu).

Curriculum Vitae

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