1) S. C. Smith, "Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum," The 2006 ASEE Midwest Section Annual Conference, September 2006.

2) S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, "Optimization of NULL Convention Self-Timed Circuits," Integration, The VLSI Journal, Vol. 37/3, pp. 135-165, August 2004.

3) S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "Delay-Insensitive Gate-Level Pipelining," Integration, the VLSI Journal, Vol. 30/2, pp. 103-131, October 2001.

4) S. C. Smith, "Speedup of NULL Convention Digital Circuits Using NULL Cycle Reduction," Journal of Systems Architecture, Vol. 52/7, pp. 411-422, July 2006.

5) S. C. Smith, "Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput," The 2004 International Conference on VLSI, pp. 407-412, June 2004.

6) S. C. Smith, "Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-wise Completion Strategy," The 2003 International Conference on VLSI, pp. 143-149, June 2003.

7) S. C. Smith, "Speedup of Self-Timed Digital Systems Using Early Completion," The IEEE Computer Society Annual Symposium on VLSI, pp. 107-113, April 2002.

8) S. K. Bandapati, S. C. Smith, and M. Choi, "Design and Characterization of NULL Convention Self-Timed Multipliers," IEEE Design and Test of Computers: Special Issue on Clockless VLSI Design, Vol. 30/6, pp. 26-36, November-December 2003.     Figures

9) S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "NULL Convention Multiply and Accumulate Unit with Conditional Rounding, Scaling, and Saturation," Journal of Systems Architecture, Vol. 47/12, pp. 977-998, June 2002.

10) S. C. Smith, "Development of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit," Integration, The VLSI Journal, Vol. 39/1, pp. 12-28, September 2005.

11) S. C. Smith, "Design of a NULL Convention Self-Timed Divider," The 2004 International Conference on VLSI, pp. 447-453, June 2004.

12) S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," The 2003 International Conference on VLSI, pp. 178-184, June 2003.

13) B. Bhaskaran, V. Satagopan, and S. C. Smith, "High-Speed Energy Estimation for Delay-Insensitive Circuits," The 2005 International Conference on Computer Design, pp. 35-41, June 2005.

14) A. Singh and S. C. Smith, "Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation," The 2005 International Conference on Computer Design, pp. 115-121, June 2005.

15) V. Satagopan, B. Bhaskaran, W. Al-Assadi, and S. C. Smith, "Automation in Design for Test for Asynchronous NULL Conventional Logic (NCL) Circuits," 12th NASA Symposium on VLSI Design, October, 2005.

16) B. Bhaskaran, V. Satagopan, W. Al-Assadi, and S. C. Smith, "Implementation of Design For Test for Asynchronous NCL Designs," The 2005 International Conference on Computer Design, pp. 78-84, June 2005.