-- delays based on physical-level simulations of static gates designed with 1.8V, 0.18um technology

  ------------------------------------- 
  -- invx0 
  ------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity invx0 is 
      port(i: in std_logic; 
           zb: out std_logic); 
  end invx0; 

  architecture archinvx0 of invx0 is 
  begin 
      invx0: process(i) 
      begin 
        if i = '0' then 
           zb <= '1' after 15.91 ps; 
        elsif i = '1' then 
           zb <= '0' after 8.87 ps; 
        else 
           zb <= not i; 
        end if; 
      end process; 
  end archinvx0; 


  ------------------------------------- 
  -- th12bx0 
  ------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th12bx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           zb: out std_logic); 
  end th12bx0; 

  architecture archth12bx0 of th12bx0 is 
  begin 
     th12bx0: process(a, b) 
     begin 
        if a = '0' and b = '0' then 
           zb <= '1' after 59.2 ps; 
        elsif a = '1' or b = '1' then 
           zb <= '0' after 15.175 ps; 
        else 
           zb <= a nor b; 
        end if; 
     end process; 
  end archth12bx0; 


  ----------------------------------------------------------- 
  -- th12x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th12x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           z: out std_logic); 
  end th12x0; 

  architecture archth12x0 of th12x0 is 
  begin 
     th12x0: process(a, b) 
     begin 
        if a = '0' and b = '0' then 
           z <= '0' after 113.26 ps; 
        elsif a = '1' or b = '1' then 
           z <= '1' after 54.2 ps; 
        else 
           z <= a or b; 
       end if; 
     end process; 
  end archth12x0; 


  ------------------------------------- 
  -- th13bx0 
  ------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th13bx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           zb: out std_logic); 
  end th13bx0; 

  architecture archth13bx0 of th13bx0 is 
  begin 
     th13bx0: process(a,b,c) 
     begin 
        if a = '0' and b = '0' and c= '0' then 
           zb <= '1' after 124.25 ps; 
        elsif a = '1' or b = '1' or c= '1' then 
           zb <= '0' after 16.23 ps; 
        else 
           zb <= not(a or b or c); 
        end if; 
     end process; 
  end archth13bx0; 


  ----------------------------------------------------------- 
  -- th13x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th13x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           z: out std_logic); 
  end th13x0; 

  architecture archth13x0 of th13x0 is 
  begin 
     th13x0: process(a, b, c) 
     begin 
        if a = '0' and b = '0' and c = '0' then 
           z <= '0' after 192.34 ps; 
        elsif a = '1' or b = '1' or c = '1' then 
           z <= '1' after 54.67 ps; 
        else 
           z <= a or b or c; 
        end if; 
     end process; 
  end archth13x0; 


  ----------------------------------------------------------- 
  -- th14bx0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th14bx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           zb: out std_logic); 
  end th14bx0; 

  architecture archth14bx0 of th14bx0 is 
  begin 
     th14bx0: process(a, b, c, d) 
     begin 
        if a = '0' and b = '0' and c = '0' and d = '0' then 
           zb <= '1' after 172 ps; 
        elsif a = '1' or b = '1' or c = '1' or d = '1' then 
           zb <= '0' after 19.16 ps; 
        else 
           zb <= not(a or b or c or d); 
        end if; 
     end process; 
  end archth14bx0; 


  ----------------------------------------------------------- 
  -- th14x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th14x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic); 
  end th14x0; 

  architecture archth14x0 of th14x0 is 
  begin 
     th14x0: process(a, b, c, d) 
     begin 
        if a = '0' and b = '0' and c = '0' and d = '0' then 
           z <= '0' after 258.1 ps; 
        elsif a = '1' or b = '1' or c = '1' or d = '1' then 
           z <= '1' after 66.02 ps; 
        else 
           z <= a or b or c or d; 
        end if; 
     end process; 
  end archth14x0; 


  ----------------------------------------------------------- 
  -- th22dx0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th22dx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           rst: in std_logic; 
           z: out std_logic ); 
  end th22dx0; 

  architecture archth22dx0 of th22dx0 is 
  begin 
     th22dx0: process(a, b, rst) 
     begin 
        if rst = '1' then -- reset 
           z <= '1' after 105.03 ps; 
        elsif (a= '1' and b= '1') then 
           z <= '1' after 138.92 ps; 
        elsif  (a= '0' and b= '0') then 
           z <= '0' after 275.9 ps; 
        end if; 
     end process; 
  end archth22dx0; 


  ----------------------------------------------------------- 
  -- th22nx0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th22nx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           rst: in std_logic; 
           z: out std_logic ); 
  end th22nx0; 

  architecture archth22nx0 of th22nx0 is 
  begin 
     th22nx0: process(a, b, rst) 
     begin 
        if rst = '1' then -- reset 
           z <= '0' after 187.7 ps; 
        elsif (a= '1' and b= '1') then 
           z <= '1' after 172.3 ps; 
        elsif  (a= '0' and b= '0') then 
           z <= '0' after 211.9 ps; 
        end if; 
     end process; 
  end archth22nx0; 


  ----------------------------------------------------------- 
  -- th22x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th22x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           z: out std_logic ); 
  end th22x0; 

  architecture archth22x0 of th22x0 is 
  begin 
     th22x0: process(a, b) 
     begin 
        if (a= '1' and b= '1') then 
           z <= '1' after 127.85 ps; 
        elsif  (a= '0' and b= '0') then 
           z <= '0' after 193.9 ps; 
        end if; 
     end process; 

  end archth22x0; 


  ----------------------------------------------------------- 
  -- th23w2x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th23w2x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; 
           c: in std_logic; 
           z: out std_logic ); 
  end th23w2x0; 

  architecture archth23w2x0 of th23w2x0 is 
  begin 
     th23w2x0: process(a, b, c) 
     begin 
        if (a= '0' and b= '0' and c= '0') then 
           z <= '0' after 285.9 ps; 
        elsif  (a= '1' or (b= '1' and c= '1')) then 
           z <= '1' after 123.26 ps; 
        end if; -- else NULL 
     end process; 
  end archth23w2x0; 
          

  ----------------------------------------------------------- 
  -- th23x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th23x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           z: out std_logic ); 
  end th23x0; 

  architecture archth23x0 of th23x0 is 
  begin 
     th23x0: process(a, b, c) 
     begin 
        if (a= '0' and b= '0' and c= '0') then 
           z <= '0' after 318.76 ps; 
        elsif  (a= '1' and b= '1') or (b= '1' and c= '1') or (c= '1' and a= '1') then 
           z <= '1' after 155.18 ps; 
        end if; 
     end process; 
    
  end archth23x0; 


  ----------------------------------------------------------- 
  -- th24x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th24x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th24x0; 

  architecture archth24x0 of th24x0 is 
  begin 
     th24x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 418.3 ps; 
        elsif  ((a= '1' and b= '1') or (a= '1' and c= '1') or (a= '1' and d= '1') 
                or (b= '1' and c= '1') or (b= '1' and d= '1') or (c= '1' and d = '1')) then 
           z <= '1' after 193.35 ps; 
        end if; -- else NULL 
     end process; 
  end archth24x0; 


  ----------------------------------------------------------- 
  -- th24w22x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th24w22x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; -- weight 2 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th24w22x0; 

  architecture archth24w22x0 of th24w22x0 is 
  begin 
     th24w22x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 462.88 ps; 
        elsif  (a= '1' or b= '1' or (c= '1' and d = '1')) then 
           z <= '1' after 193.4 ps; 
        end if; -- else NULL 
     end process; 
  end archth24w22x0; 


  ----------------------------------------------------------- 
  -- th24w2x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th24w2x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th24w2x0; 

  architecture archth24w2x0 of th24w2x0 is 
  begin 
     th24w2x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 462.88 ps; 
        elsif  (a= '1' or (b= '1' and c= '1') or (b= '1' and d = '1') or 
               (c= '1' and d= '1')) then 
           z <= '1' after 193.42 ps; 
        end if; -- else NULL 
     end process; 
  end archth24w2x0; 


  ----------------------------------------------------------- 
  -- th33dx0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th33dx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           rst: in std_logic; 
           z: out std_logic ); 
  end th33dx0; 

  architecture archth33dx0 of th33dx0 is 
  begin 
     th33dx0: process(a, b, c, rst) 
     begin 
        if rst = '1' then 
            z <= '1' after 117.61 ps; 
        elsif (a= '1' and b= '1' and c= '1') then 
           z <= '1' after 180.2 ps; 
        elsif  (a= '0' and b= '0' and c= '0') then 
           z <= '0' after 373.86 ps; 
        end if; -- else NULL 
     end process; 
  end archth33dx0; 


  ----------------------------------------------------------- 
  -- th33nx0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th33nx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           rst: in std_logic; 
           z: out std_logic ); 
  end th33nx0; 

  architecture archth33nx0 of th33nx0 is 
  begin 
     th33nx0: process(a, b, c, rst) 
     begin 
        if rst = '1' then 
            z <= '0' after 216.15 ps; 
        elsif (a= '1' and b= '1' and c= '1') then 
           z <= '1' after 241.77 ps; 
        elsif  (a= '0' and b= '0' and c= '0') then 
           z <= '0' after 348.46 ps; 
        end if; -- else NULL 
     end process; 
  end archth33nx0; 


  ----------------------------------------------------------- 
  -- th33x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th33x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           z: out std_logic ); 
  end th33x0; 

  architecture archth33x0 of th33x0 is 
  begin 
     th33x0: process(a, b, c) 
     begin 
        if (a= '1' and b= '1' and c= '1') then 
           z <= '1' after 158.99 ps; 
        elsif  (a= '0' and b= '0' and c= '0') then 
           z <= '0' after 253.63 ps; 
        end if; -- else NULL 
     end process; 
  end archth33x0; 


  ----------------------------------------------------------- 
  -- th33w2x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th33w2x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; 
           c: in std_logic; 
           z: out std_logic ); 
  end th33w2x0; 

  architecture archth33w2x0 of th33w2x0 is 
  begin 
     th33w2x0: process(a, b, c) 
     begin 
        if (a= '0' and b= '0' and c= '0') then 
           z <= '0' after 278.68 ps; 
        elsif  (a= '1' and (b= '1' or c= '1')) then 
           z <= '1' after 136.6 ps; 
        end if; -- else NULL 
     end process; 
  end archth33w2x0; 


  ----------------------------------------------------------- 
  --th34w22x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th34w22x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; -- weight 2 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th34w22x0; 

  architecture archth34w22x0 of th34w22x0 is 
  begin 
     th34w22x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 460.24 ps; 
        elsif  (a = '1' and b = '1') or (a = '1' and c = '1')  or (a = '1' and d = '1') 
                    or (b = '1' and c = '1') or (b = '1' and d = '1') then 
           z <= '1' after 201.93 ps; 
        end if; -- else NULL 
     end process; 
  end archth34w22x0; 


  ----------------------------------------------------------- 
  --th34w2x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th34w2x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th34w2x0; 

  architecture archth34w2x0 of th34w2x0 is 
  begin 
     th34w2x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 494.49 ps; 
        elsif  (a = '1' and b = '1') 
                    or (a = '1' and c = '1') 
                    or (a = '1' and d = '1') 
                    or (b = '1' and c = '1' and d = '1') then 
           z <= '1' after 189.6 ps; 
        end if; -- else NULL 
     end process; 
  end archth34w2x0; 


  ----------------------------------------------------------- 
  -- th34w32x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th34w32x0 is 
      port(a: in std_logic; -- weight 3 
           b: in std_logic; -- weight 2 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th34w32x0; 

  architecture archth34w32x0 of th34w32x0 is 
  begin 
     th34w32x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 386.31 ps; 
        elsif  (a= '1' or (b= '1' and (c= '1' or d = '1') ) ) then 
           z <= '1' after 146.95 ps; 
        end if; -- else NULL 
     end process; 
  end archth34w32x0; 


  ----------------------------------------------------------- 
  -- th34w3x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th34w3x0 is 
      port(a: in std_logic; -- weight 3 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th34w3x0; 

  architecture archth34w3x0 of th34w3x0 is 
  begin 
     th34w3x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 388.84 ps; 
        elsif  (a= '1' or (b= '1' and c= '1' and d = '1')) then 
           z <= '1' after 168.8 ps; 
        end if; -- else NULL 
     end process; 
  end archth34w3x0; 


  ----------------------------------------------------------- 
  -- th34x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th34x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th34x0; 

  architecture archth34x0 of th34x0 is 
  begin 
     th34w3x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 535.96 ps; 
        elsif ((a= '1' and b= '1' and c= '1') or 
               (a= '1' and c= '1' and d= '1') or 
               (a= '1' and b= '1' and d= '1') or 
               (b= '1' and c= '1' and d= '1')) then 
           z <= '1' after 276.83 ps; 
        end if; -- else NULL 
     end process; 
  end archth34x0; 


  ----------------------------------------------------------- 
  -- th44x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th44x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th44x0; 

  architecture archth44x0 of th44x0 is 
  begin 
     th44x0: process(a, b, c, d) 
     begin 
        if (a= '1' and b= '1' and c= '1' and d= '1') then 
           z <= '1' after 249.04 ps; 
        elsif  (a= '0' and b= '0' and c= '0' and d= '0') then 
           z <= '0' after 452.72 ps; 
        end if; -- else NULL 
     end process; 
  end archth44x0; 


  ----------------------------------------------------------- 
  -- th44w22x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th44w22x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; -- weight 2 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th44w22x0; 

  architecture archth44w22x0 of th44w22x0 is 
  begin 
     th44w22x0: process(a, b, c, d) 
     begin 
        if ((a= '1' and b= '1') or 
            (a= '1' and c= '1' and d= '1') or 
            (b= '1' and c= '1' and d= '1')) then 
           z <= '1' after 204.54 ps; 
        elsif  (a= '0' and b= '0' and c= '0' and d= '0') then 
           z <= '0' after 436.82 ps; 
        end if; -- else NULL 
     end process; 
  end archth44w22x0; 


  ----------------------------------------------------------- 
  -- th44w2x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th44w2x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th44w2x0; 

  architecture archth44w2x0 of th44w2x0 is 
  begin 
     th44w2x0: process(a, b, c, d) 
     begin 
        if ((a= '1' and b= '1' and c= '1') or 
            (a= '1' and b= '1' and d= '1') or 
            (a= '1' and c= '1' and d= '1')) then 
           z <= '1' after 248.23 ps; 
        elsif  (a= '0' and b= '0'and c= '0' and d= '0') then 
           z <= '0' after 433.42 ps; 
        end if; -- else NULL 
     end process; 
  end archth44w2x0; 


  ----------------------------------------------------------- 
  -- th44w322x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th44w322x0 is 
      port(a: in std_logic; -- weight 3 
           b: in std_logic; -- weight 2 
           c: in std_logic; -- weight 2 
           d: in std_logic; 
           z: out std_logic ); 
  end th44w322x0 ; 

  architecture archth44w322x0 of th44w322x0 is 
  begin 
     th44w322x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 411.33 ps; 
        elsif  ( a = '1' and ( b = '1' or c = '1' or d = '1')) or ( b = '1' and c = '1' ) then 
           z <= '1' after 165.94 ps; 
        end if; -- else NULL 
     end process; 
  end archth44w322x0; 


  ----------------------------------------------------------- 
  -- th44w3x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th44w3x0 is 
      port(a: in std_logic; -- weight 3 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th44w3x0; 

  architecture archth44w3x0 of th44w3x0 is 
  begin 
     th44w3x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 317.43 ps; 
        elsif a = '1' and ( b = '1' or c = '1' or d = '1' ) then 
           z <= '1' after 130.36 ps; 
        end if; -- else NULL 
     end process; 
  end archth44w3x0 ; 


  ----------------------------------------------------------- 
  -- th54w22x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th54w22x0 is 
      port(a: in std_logic; -- weight 2 
           b: in std_logic; -- weight 2 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th54w22x0; 

  architecture archth54w22x0 of th54w22x0 is 
  begin 
     th54w22x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 388.41 ps; 
        elsif  (a= '1' and b= '1' and (c= '1' or d = '1')) then 
           z <= '1' after 196.2 ps; 
        end if; -- else NULL 
     end process; 
  end archth54w22x0; 


  ----------------------------------------------------------- 
  -- th54w322x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th54w322x0 is 
      port(a: in std_logic; -- weight 3 
           b: in std_logic; -- weight 2 
           c: in std_logic; -- weight 2 
           d: in std_logic; 
           z: out std_logic ); 
  end th54w322x0; 

  architecture archth54w322x0 of th54w322x0 is 
  begin 
     th54w322x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0'and c= '0' and d = '0') then 
           z <= '0' after 401.32 ps; 
        elsif  (a= '1' and b= '1') or (a = '1' and c= '1') or 
               (b= '1' and c='1' and d= '1') then 
           z <= '1' after 173.11 ps; 
        end if; -- else NULL 
     end process; 
  end archth54w322x0; 


  ----------------------------------------------------------- 
  -- th54w32x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th54w32x0 is 
      port(a: in std_logic; -- weight 3 
           b: in std_logic; -- weight 2 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th54w32x0; 

  architecture archth54w32x0 of th54w32x0 is 
  begin 
     th54w32x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 440.25 ps; 
        elsif  (a= '1' and b= '1') or (a = '1' and c= '1' and d = '1') then 
           z <= '1' after 204.51 ps; 
        end if; -- else NULL 
     end process; 
  end archth54w32x0; 


  ----------------------------------------------------------- 
  -- thand0x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity thand0x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end thand0x0; 

  architecture archthand0x0 of thand0x0 is 
  begin 
     thand0x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 433.29 ps; 
        elsif  ((a = '1' and b = '1') or (b = '1' and c = '1') or (a = '1' and d = '1')) then 
           z <= '1' after 151.55 ps; 
        end if; -- else NULL 
     end process; 
  end archthand0x0; 


  ----------------------------------------------------------- 
  -- th24compx0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity th24compx0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end th24compx0; 

  architecture archth24compx0 of th24compx0 is 
  begin 
     th24compx0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 303.32 ps; 
        elsif  (a = '1' or b = '1') and (c = '1' or d = '1') then 
           z <= '1' after 135.1 ps; 
        end if; -- else NULL 
     end process; 
  end archth24compx0; 


  ----------------------------------------------------------- 
  -- thxor0x0      
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity thxor0x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           c: in std_logic; 
           d: in std_logic; 
           z: out std_logic ); 
  end thxor0x0; 

  architecture archthxor0x0 of thxor0x0 is 
  begin 
     thxor0x0: process(a, b, c, d) 
     begin 
        if (a= '0' and b= '0' and c= '0' and d = '0') then 
           z <= '0' after 376.14 ps; 
        elsif  (a = '1' and b = '1') or (c = '1' and d = '1') then 
           z <= '1' after 162 ps; 
        end if; -- else NULL 
     end process; 
  end archthxor0x0; 
  
  
  
  ----------------------------------------------------------- 
  -- and2x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity and2x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
           z: out std_logic ); 
  end and2x0; 

  architecture archand2x0 of and2x0 is 
  begin 
     and2x0: process(a,b) 
     begin 
        if (a= '1' and b= '1') then 
           z <= '1' after 69.93 ps; 
        elsif (a= '0' or b= '0') then
           z <= '0' after 69.45 ps; 
        end if; 
     end process; 
  end archand2x0; 
  
  
  
  ----------------------------------------------------------- 
  -- and3x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity and3x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
	   c: in std_logic;
           z: out std_logic ); 
  end and3x0; 

  architecture archand3x0 of and3x0 is 
  begin 
     and3x0: process(a,b,c) 
     begin 
        if (a= '1' and b= '1' and c= '1') then 
           z <= '1' after 106.96 ps; 
        elsif (a= '0' or b= '0' or c= '0') then
           z <= '0' after 86.75 ps; 
        end if; 
     end process; 
  end archand3x0; 
  
  
  
   ----------------------------------------------------------- 
  -- and4x0 
  ----------------------------------------------------------- 
  library ieee; 
  use ieee.std_logic_1164.all; 

  entity and4x0 is 
      port(a: in std_logic; 
           b: in std_logic; 
	   c: in std_logic;
	   d: in std_logic;
           z: out std_logic ); 
  end and4x0; 

  architecture archand4x0 of and4x0 is 
  begin 
     and4x0: process(a,b,c,d) 
     begin 
        if (a= '1' and b= '1' and c= '1' and d= '1') then 
           z <= '1' after 105.13 ps; 
        elsif (a= '0' or b= '0' or c= '0' or d= '0') then
           z <= '0' after 74.78 ps; 
        end if;
     end process; 
  end archand4x0;  

  --------------------------------------------------------