Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum Throughout the Nation

Overview

The development of synchronous circuits currently dominates the semiconductor design industry. However, there are major limiting factors to the synchronous, clocked approach, including the increasing difficulty of clock distribution, increasing clock rates, decreasing feature size, increasing power consumption, timing closure effort, and difficulty with design reuse. Asynchronous (clockless) circuits require less power, generate less noise, produce less electro-magnetic interference (EMI), and allow for easier reuse of components, compared to their synchronous counterparts, without compromising performance. As the demand continues for designs with higher performance, higher complexity, and decreased feature size, asynchronous paradigms will become more widely used in the industry, as evidenced by the 2003 and 2007 International Technology Roadmap for Semiconductors’ (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues. The 2008 ITRS shows that asynchronous circuits account for 11% of chip area in 2008, compared to 7% in 2007, and estimates they will account for 23% of chip area by 2014, and 35% of chip area by 2019. Therefore, it is extremely important for Computer Engineering students to be introduced to asynchronous paradigms to make them more marketable and more prepared for the challenges faced by the digital design community for years to come.

Objectives

The goal of this project is to improve educational practices and student learning through development of materials that provide for easy integration of asynchronous concepts into existing course structures. No readily available educational materials currently exist for this topic. Following are the project's specific objectives:

  • Develop lecture notes, example problems, and group projects to introduce asynchronous paradigms,
  • Develop a VHDL library of fundamental asynchronous gates and components,
  • Develop static and semi-static transistor-level libraries of fundamental asynchronous gates,
  • Develop static and semi-static physical-level libraries of fundamental asynchronous gates,
  • Develop a Design-For-Test (DFT) library of fundamental asynchronous gates,
  • Develop NCL design and optimization CAD tools,
  • Develop an asynchronous FPGA
  • Integrate the developed materials into undergraduate-level courses at University of Arkansas, Missouri University of Science and Technology, and other institutions, and
  • Broadly disseminate the developed materials to faculty members at other institutions.
The developed materials will integrate cutting-edge technology into standard educational practices, to provide a low-cost, innovative addition to the Computer Engineering curriculum. The design modules focus on the delay-insensitive NULL Convention Logic (NCL) paradigm.

VHDL Library

VLSI Libraries

Mentor Graphics Libraries: 1.8V, 0.18um TSMC CMOS process

Cadence Libraries: 3.3V, 0.5um IBM 5AM BiCMOS process

Course Modules

  1. Intro to Asynchronous Logic:  Slides
  2. Intro to NCL:  Slides
  3. Transistor-Level NCL Gate Design:  Slides | Example Problems
  4. Input-Completeness and Observability:  Slides | Example Problems
  5. Dual-Rail NCL Design:  Slides | Example Problems
  6. Quad-Rail NCL Design:  Slides | Example Problems
  7. NCL Throughput Optimization:  Slides | Example Problems
  8. NCL Low Power Design:  Slides | Example Problems
  9. Group Projects
Professors: Please send us an email and we will gladly provide you with solutions to the example problems.

NCL Book

Scott C. Smith and Jia Di, Designing Asynchronous Circuits using NULL Convention Logic (NCL), Synthesis Lectures on Digital Circuits and Systems, Vol. 4/1, July 2009, Morgan & Claypool Publishers (doi: 10.2200/S00202ED1V01Y200907DCS023).

NCL Publications

  1. S. C. Smith, W. K. Al-Assadi, and J. Di, "Integrating Asynchronous Digital Design into the Computer Engineering Curriculum," accepted for publication in IEEE Transactions on Education.
  2. A. Bailey, A. Al Zahrani, G. Fu, J. Di, and S. C. Smith, "Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power,” Journal of Low Power Electronics, Vol. 4/3, pp. 337-348, December 2008.
  3. V. Satagopan, B. Bhaskaran, A. Singh, and S. C. Smith, "Energy Calculation and Estimation for Delay-Insensitive Digital Circuits," Elsevier’s Microelectronics Journal, Vol. 38/10-11, pp. 1095-1107, October/November 2007.
  4. V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, S. C. Smith, and S. Kakarla, "DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits," IEEE Transactions on VLSI Systems: Special Issue on System on Chip Integration, Vol. 15/10, pp. 1155-1159, October 2007.
  5. S. C. Smith, "Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits," IEEE Transactions on VLSI Systems, Vol. 15/6, June 2007.
  6. S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," Elsevier's Microelectronic Engineering Journal: Special Issue on VLSI Design and Test, Vol. 84/2, pp. 280-287, February 2007.
  7. S. C. Smith, "Speedup of NULL Convention Digital Circuits Using NULL Cycle Reduction," Elsevier's Journal of Systems Architecture, Vol. 52/7, pp. 411-422, July 2006.
  8. S. C. Smith, "Development of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit," Elsevier's Integration, The VLSI Journal, Vol. 39/1, pp. 12-28, September 2005.
  9. S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, "Optimization of NULL Convention Self-Timed Circuits," Elsevier's Integration, The VLSI Journal, Vol. 37/3, pp. 135-165, August 2004.
  10. S. K. Bandapati, S. C. Smith, and M. Choi, "Design and Characterization of NULL Convention Self-Timed Multipliers," IEEE Design and Test of Computers: Special Issue on Clockless VLSI Design, Vol. 30/6, pp. 26-36, November-December 2003. Figures
  11. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "NULL Convention Multiply and Accumulate Unit with Conditional Rounding, Scaling, and Saturation," Elsevier's Journal of Systems Architecture, Vol. 47/12, pp. 977-998, June 2002.
  12. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "Delay-Insensitive Gate-Level Pipelining," Elsevier's Integration, the VLSI Journal, Vol. 30/2, pp. 103-131, October 2001.
  13. L. Zhou and S. C. Smith, “Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit,” IEEE Midwest Symposium on Circuits and Systems, pp. 499-502, August 2009.
  14. A. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, "Ultra-Low Power Delay-Insensitive Circuit Design,” IEEE Midwest Symposium on Circuits and Systems, August 2008.
  15. B. Hollosi, M. Barlow, G. Fu, C. Lee, J. Di, S. C. Smith, H. A. Mantooth, and M. Schupbach, "Delay-Insensitive Asynchronous ALU for Cryogenic Temperature Environments,” IEEE Midwest Symposium on Circuits and Systems, August 2008.
  16. S. C. Smith and W. K. Al-Assadi, "Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum," 6th ASEE Global Colloquium on Engineering Education, October 2007.
  17. S. C. Smith and W. K. Al-Assadi, "Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum," The 2007 ASEE Annual Conference & Exposition, June 2007.
  18. S. C. Smith, "Design of a Logic Element for Implementing an Asynchronous FPGA," 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 13-22, February 2007.
  19. S. C. Smith and W. K. Al-Assadi, "Teaching Asynchronous Digital Design in the Undergraduate Computer Engineering Curriculum," IEEE Region 5 Technical Conference, April 2007.
  20. M. V. Joshi, S. Gosavi, V. Jagadeesan, A. Basu, S. Jaiswal, W. K. Al-Assadi, and S. C. Smith, "NCL Implementation of Dual-Rail 2s Complement 8×8 Booth2 Multiplier using Static and Semi-Static Primitives," IEEE Region 5 Technical Conference, April 2007.
  21. S. R. Mallepalli, S. Kakarla, S. Burugapalli, S. Beerla, S. Kotla, P. K. Sunkara, W. K. Al-Assadi, and S. C Smith, "Implementation of Static and Semi-Static Versions of a Quad-Rail NCL 24+8x8 Multiply and Accumulate Unit," IEEE Region 5 Technical Conference, April 2007.
  22. R. S. P. Nair, F. Kacani, R. Bonam, S. M. Gandla, S. K. Chitneni, V. Kadiyala, W. K. Al-Assadi, and S. C. Smith, "Implementation of Static and Semi-Static Versions of a Bit-Wise Pipelined Dual-Rail NCL 2s Complement Multiplier," IEEE Region 5 Technical Conference, April 2007.
  23. S. C. Smith, "Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum," The 2006 ASEE Midwest Section Annual Conference, September 2006.
  24. V. Satagopan, B. Bhaskaran, W. Al-Assadi, and S. C. Smith, "Automation in Design for Test for Asynchronous Null Conventional Logic (NCL) Circuits," 12th NASA Symposium on VLSI Design, October, 2005.
  25. B. Bhaskaran, V. Satagopan, and S. C. Smith, "High-Speed Energy Estimation for Delay-Insensitive Circuits," The 2005 International Conference on Computer Design, pp. 35-41, June 2005.
  26. A. Singh and S. C. Smith, "Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation," The 2005 International Conference on Computer Design, pp. 115-121, June 2005.
  27. B. Bhaskaran, V. Satagopan, W. Al-Assadi, and S. C. Smith, "Implementation of Design For Test for Asynchronous NCL Designs," The 2005 International Conference on Computer Design, pp. 78-84, June 2005.
  28. S. C. Smith, "Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput," The 2004 International Conference on VLSI, pp. 407-412, June 2004.
  29. S. C. Smith, "Design of a NULL Convention Self-Timed Divider," The 2004 International Conference on VLSI, pp. 447-453, June 2004.
  30. S. C. Smith, "Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-wise Completion Strategy," The 2003 International Conference on VLSI, pp. 143-149, June 2003.
  31. S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," The 2003 International Conference on VLSI, pp. 178-184, June 2003.
  32. S. C. Smith, "Speedup of Self-Timed Digital Systems Using Early Completion," The IEEE Computer Society Annual Symposium on VLSI, pp. 107-113, April 2002.
  33. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction," The 10th International Workshop on Logic and Synthesis, pp. 185-189, June 2001.

People

Principle Investigator: Scott C. Smith

Co-Principle Investigators: Jia Di and Waleed K. Al-Assadi

Graduate Assistants:

  • Bonita Bhaskaran, PhD
  • Mandar Joshi, MS
  • Sindhu Kakarla, MS
  • Samarsen Mallepalli, MS
  • Ravi Parameswaran, PhD/MS
  • Vijay Pillai, MS
  • Venkat Satagopan, PhD
  • Vipin Sharma, MS
  • Steven Yancey, PhD

Sponsor: National Science Foundation



The PIs gratefully acknowledge the support from the National Science Foundation under CCLI grants DUE-0536343, DUE-0717572, and DUE-0717767.

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.

Contact Us

3218 Bell Engineering Center
Fayetteville, AR 72701
Phone: (479) 575-6047 or (479) 575-6587
Fax: (479) 575-7967
E-Mail: smithsco@uark.edu