Trustable Digital Circuit Design Lab

 

Publications

 

·         Patents

1.     US Patent: S. C. Smith, J. Di, J. Frenkil, A. Arthurs, and R. Foster, Single Component Sleep-Convention Logic (SCL) Modules, US Patent: 9,094,013 B2, July 28, 2015

2.     US Patent: S. C. Smith and J. Di, Multi-Threshold Sleep Convention Logic without NSleep, US Patent: 9,083,337, B2, July 14, 2015

3.     US Patent: J. Di and S. C. Smith, Ultra-Low Power Multi-Threshold Asynchronous Circuit Design, US Patent: 8,664,977 B2, March 4, 2014

4.     US Patent: J. Di and S. C. Smith, Ultra-Low Power Multi-Threshold Asynchronous Circuit Design, US Patent: 8,207,758 B2, June 26, 2012

5.     US Patent: J. Di and S. C. Smith, Ultra-Low Power Multi-Threshold Asynchronous Circuit Design, US Patent: 7,977,972 B2, July 12, 2011

 

·         Books and Book Chapters

1.     S. C. Smith and J. Di, Designing Asynchronous Circuits using NULL Convention Logic (NCL), Morgan & Claypool Publishers, 2009

2.     J. Di and S. C. Smith, Chapter 58: Asynchronous Digital Circuits, Extreme Environment Electronics, CRC Press, 2012

3.     J. Di and D. R. Thompson, Chapter 12: Security for RFID Tags, Introduction to Hardware Security and Trust, page 283-304, Springer, 2011

4.     J. Di and P. K. Lala, Chapter 7: Cellular Array-Based Delay-Insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems, Emerging Nanotechnologies, page 203-226, ISBN 978-0-387-74746-0, Springer

 

·         Journal papers

1.     A. Rahman, S. Roy, R. Kotecha, R. Murphree, K. Addington, A. Abbasi, H. A. Mantooth, J. Di, M. Francis, and J. Holmes, “High Temperature SiC CMOS Comparator and Op Amp for Protection Circuits in Voltage Regulators and Switch-Mode Converters,” accepted by IEEE Journal of Emerging and Selected Topics in Power Electronics

2.     N. Kuhns, L. Caley, A. Rahman, S. Ahmed, J. Di, H. A. Mantooth, A. M. Francis, and J. Holmes, “Complex High-Temperature CMOS Silicon Carbide Digital Circuit Designs,” IEEE Transactions on Device and Materials Reliability, Vol. 16, Issue 2, pp. 105-111, February 2016

3.     L. Zhou, S. C. Smith, and J. Di, “Radiation Hardened NULL Convention Logic Asynchronous Circuit Design,” Journal of Low Power Electronics and Applications, vol. 5, issue 4, pp. 216-233, October 2015

4.     R. Nair, S. C. Smith, and J. Di, “Delay Insensitive Ternary CMOS Logic for Secure Hardware,” Journal of Low Power Electronics and Applications, vol. 5, issue 3, pp. 183-215, September 2015

5.     L. Zhou, R. Parameswaran, F. A. Parsan, S. C. Smith, and J. Di, “Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology,” Journal of Low Power Electronics and Applications, vol. 5, issue 2, pp. 81-100, May 2015

6.     L. Men and J. Di, “Asynchronous Parallel Platforms with Balanced Performance and Energy,” Journal of Low Power Electronics, Vol. 10, No. 4, pp. 566-579, 2014

7.     M. Linder, J. Di, and S. C. Smith, “Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L) – a Low Overhead Secure IC Design Methodology,” Journal of Low Power Electronics and Applications, Vol. 3, Issue 4, pp. 300-306, 2014

8.     D. Thompson, J. Di, and M. Daugherty, “Teaching RFID Information Systems Security,” IEEE Transactions on Education, Vol. 57, Issue 1, pp. 42-47, 2014

9.     M. Hinds, B. Sparkman, J. Di, and S. C. Smith, “An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency,” Journal of Low Power Electronics, Vol. 9, No. 2, pp. 175-188, 2013

10. W. Cilio, M. Linder, C. Porter, J. Di, D. R. Thompson, and S. C. Smith, “Mitigating Power- and Timing-based Side-Channel Attacks Using Dual-Spacer Dual-Rail Delay-Insensitive Asynchronous Logic,” Elsevier Microelectronics Journal, Vol. 4, Issue 3, pp. 258-269, 2013

11. J. Yust, M. Hinds, and J. Di, “Structural Checking: Detecting Malicious Logic without a Golden Reference,” Journal of Computational Intelligence and Electronic Systems, Vol. 1, No. 2, pp. 169-177, 2012

12. A. Arthurs, J. Roark, and J. Di, “A Comparative Study of Ultra-Low Voltage Digital Circuit Design,” International Journal of VLSI Design & Communication Systems, Vol. 3, No. 3, June 2012

13. S. Periaswamy, D. Thompson, and J. Di, “Fingerprinting RFID Tags,” IEEE Transactions on Dependable and Secure Computing, Vol. 8, No. 6, pp. 938-943, 2011

14. D. Coleman and J. Di, “Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime,” Journal of Low Power Electronics, Vol. 6, NO. 2, pp. 320-324, August 2010

15. S. C. Smith, W. K. Al-Assadi, and J. Di, “Integrating Asynchronous Digital Design into the Computer Engineering Curriculum,” IEEE Transactions on Education, Vol. 53, No. 3, pp. 349-357, August 2010

16. A. Bailey, A. Al Zahrani, G. Fu, J. Di, and S. Smith, “Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power,” Journal of Low Power Electronics, Vol. 4, NO. 3, pp. 337-348, December 2008

17. R. Broughton, K. Cornett, J. Vandersand, L. Najafizadeh, H. A. Mantooth, J. Di, B. Blalock and J. Cressler, “SiGe BiCMOS Low Power Voltage Comparator for Extreme Temperature Range Applications”, International Journal of Highly Reliable Electronic Systems, Vol. 1, No. 1, pp. 13-19, January-June 2008

18. M. Barlow, V. Varadan, and J. Di, “Improvement to the Data Logging Capability of a Cough Monitoring system”, the Inquiry Undergraduate Research Journal, University of Arkansas, Vol. 8, pp. 31-35, Fall 2007

19. J. Di and P. K. Lala, "Cellular Array-based Delay-Insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems," Journal of Electronic Testing: Theory and Application, Vol. 23, NO 2-3, pp. 175-192, June 2007

20. J. Di and J. S. Yuan, "Energy-aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuits Design," Journal of Low Power Electronics, Vol. 2, NO. 2, pp. 201-216, Aug. 2006

21. J. Di, J. S. Yuan, and R. Demara, "Improving Power-awareness of Pipelined Array Multipliers using 2-Dimensional Pipeline Gating and its Application on FIR Design," Integration, the VLSI Journal, Volume 39, Issue 2, July 2006, pp. 90-112

22. J. Di and J. S. Yuan, "Energy-aware design for multi-rail encoding using NCL," IEE Proceeding on Circuits and Systems, vol. 153, pp. 100-106, April 2006

23. D. P. Vasudevan, P. K. Lala, J. Di, and J. P. Parkerson, "Reversible Logic with Online Testability," IEEE Transaction on Instrumentation and Measurement, Vol. 25, NO. 2, pp. 406-414, April 2006

24. J. S. Yuan and J. Di, "Teaching Low Power Electronic Design in Electrical and Computer Engineering," IEEE Transaction on Education, Volume: 48, Issue: 1, Feb. 2005, Pages: 169-182

25. J. Di, J. S. Yuan, and M. Hagedorn, "Input Mapping for Modeling Energy Dissipation of Complex CMOS Gates," IEE Proceedings on Circuits, Devices and Systems, Volume: 151, Issue: 4, Aug. 2004, Pages: 294 - 299.

 

·         Conference paper:

1.     J. Yang, Z. Yuan, H. Shen, X. Li, J. Di, and J. Mo, “Influence of Anode Flow Field on Mass Transport in an Air-breathing Micro Direct Methanol Fuel Cell,” accepted by the 11th IEEE Conference on Industrial Electronics and Applications (ICIEA), June 2016

2.     N. Ye, J. Yang, Z. Yuan, H. Shen, N. Zhao, J. Di, and J. Mo, “An Optimization Algorithm based on TFPA for Multiple Component Modules,” accepted by the 11th IEEE Conference on Industrial Electronics and Applications (ICIEA), June 2016

3.     H. Shen, J. Yang, Z. Yuan, N. Ye, J. Di, and J. Mo, “Research of Optimal Parameters in MOSFET Structure based on Wide Band Gap Semiconductor Material GaN,” accepted by the 28th Chinese Control and Decision Conference (CCDC), May 2016

4.     J. Habimana, F. Sabado, and J. Di, “Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic: an Improved IC Design Methodology for Side Channel Attack Mitigation,” accepted by 2016 IEEE International Symposium on Circuits & Systems (ISCAS)

5.     B. Bell, W. Bouillon, S. Li, E. Logal, and J. Di, “Application of Multi-Threshold NULL Convention Logic to Adaptive Beamforming Circuits for Ultra-Low Power,” accepted by 2016 Government Microcircuit Applications & Critical Technology Conference (GOMACTech)

6.     X. Zhang, G. Sun, Y. Zhang, W. Wu, Y. Chen, H. Li, J. Di, “A Novel PUF based on Cell Error Rate Distribution of STT-RAM,” accepted by the 21st IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2016)

7.     C. Lo, L. Men, J. Brady, and J. Di, “Asynchronous and Synchronous Designs for Low-Power FDSOI CMOS Process Optimized for Subthreshold Operation at 0.3V VDD,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2015

8.     X. Zhang, G. Sun, C. Zhang, W. Zhang, Y. Liang, T. Wang, Y. Chen, and J. Di, “Fork Path: Improving Efficiency of ORAM by Removing Redundant Memory Accesses,” the 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2015

9.     A. Li, Q. Li, V. Hu, and J. Di, “Evaluating the Capability and Performance of Access Control Policy Verification Tools,” 2015 Premier International Conference for Military Communications (MILCOM), November 2015

10. S. Chen, J. Chen, L. Wang, D. Forte, M. Tehranipoor, and J. Di, “Chip-Level Anti-Reverse Engineering using Transformable Interconnects,” the 28th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, August 2015

11. H. A. Mantooth, Y. Liu, C. Farnell, F. Zhang, Q. Li, and J. Di, “Securing DC and Hybrid Microgrids,” International Conference on DC Microgrids, June 2015

12. J. Brady, A. M. Francis, and J. Di, “Analyzing the Radiation Hardness of an NCL Library,” 24th Annual Single Event Effects (SEE) Symposium, May 2015

13. X. Zhang, G. Sun, Y. Chen, and J. Di, “err-PUF: Exploiting Cell Error Distribution for Secure NVM Authentication,” the IEEE/ACM Design Automation Conference (DAC), 2015

14. Z. Guo, D. Forte, M. Tehranipoor, and J. Di, “Investigation of Obfuscation-based Anti-Reverse Engineering for Printed Circuit Boards,” the IEEE/ACM Design Automation Conference (DAC), 2015

15. Q. Li, C. Ross, J. Yang, J. Di, J. C. Balda, and H. A. Mantooth, “The Effects of Flooding Attacks on Time-Critical Communications in the Smart Grid,” the IEEE PES Conference on Innovative Smart Grid Technologies (ISGT), 2015

16. N. Kuhns, L. Caley, A. Rahman, S. Ahmed, J. Di, H. A. Mantooth, A. M. Francis, and J. Holmes, “High Temperature Testing Results of Synchronous and Asynchronous Digital Silicon Carbide Integrated Circuits,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2015

17. J. Brady, A. M. Francis, J. Holmes, J. Di, and H. A. Mantooth, “An Asynchronous Cell Library for Operation in Wide-Temperature & Ionizing-Radiation Environments,” 2015 IEEE Aerospace Conference

18. B. Sissons, A. M. Francis, J. Holmes, H. A. Mantooth, and J. Di, “SiGe BiCMOS Comparator for Extreme Environment Applications,” 2015 IEEE Aerospace Conference

19. A. Rahman, P. D. Shepherd, S. A. Bhuyan, S. Ahmed, S. K. Akula, L. Caley, H. Alan Mantooth, J. Di, A. Matthew Francis, and J. A. Holmes, “A family of CMOS analog and mixed signal circuits in SiC for high temperature electronics,” 2015 IEEE Aerospace Conference

20. L. Men and J. Di, “An Asynchronous Finite Impulse Response Filter Design for Digital Signal Processing Unit,” IEEE Midwest Symposium on Circuits and Systems, Aug. 2014

21. L. Men and J. Di, “Framework of Scalable Delay-Insensitive Asynchronous Platform Enabling Heterogeneous Concurrency,” IEEE Midwest Symposium on Circuits and Systems, Aug. 2014

22. L. Men, B. Hollosi, and J. Di, “Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency,” IEEE International Symposium on VLSI, July 2014

23. L. Caley, C. Lo, F. Sabado, and Jia Di, “A Comparative Analysis of 3D-IC Partitioning Schemes for Asynchronous Circuits,” International Conference on IC Design and Technology, May 2014

24. J. Brady and J. Di, “Radiation-Hardened Delay-Insensitive Asynchronous Circuits,” accepted by 23rd Annual Single Event Effects (SEE) Symposium, May 2014

25. Baha A. Alsaify, Dale R. Thompson, and Jia Di, “Exploiting hidden Markov Models in identifying passive UHF RFID tags,” IEEE Radio and Wireless Symposium (RWS), Newport Beach, California, Jan. 19-22, 2014, pp. 259-261.

26. A. M. Francis, A. Rahman, J. Holmes, P. Shepherd, S. Ahmed, M. Barlow, S. Bhuyan, L. Caley, T. Moudy, H. A. Mantooth, and J. Di, “Design of Analog and Mixed-Signal Integrated SiC CMOS Circuits with a High Fidelity Process Design Kit,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2014

27. L. Caley, N. Kuhns, W. S. Bowen, P. Shepherd, A. Rahman, J. Di, H. A. Mantooth, A. M. Francis, and J. Holmes, “Delay-Insensitive Asynchronous Silicon Carbide Integrated Circuit Design for High-Temperature Applications,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2014

28. X. Zhang, C. Zhang, G. Sun, T. Zhang, and J. Di, “An Efficient Run-Time Encryption Scheme for Non-volatile Main Memory,” International Conference on Compilers Architecture and Synthesis for Embedded Systems, 2013

29. B. Sparkman, M. Hinds, J. Di, and S. C. Smith, “An Asynchronous AES Core Design for Low Power,” 2013 Semiconductor Research Corporation Annual Technical Conference

30. M. Hinds, J. Brady, M. Rothmeyer, and J. Di, “Signal Assets – a Useful Concept for Abstracting Circuit Functionality,” 2013 Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2013

31. D. Banerjee, J. Li, J. Di, and D. Thompson, “Feature Selection for RFID Tag Identification,” 7th International Conference on Communications and Networking in China, August 2012 (best paper award)

32. A. Arthurs, J. Roark, and J. Di, “Ultra-Low Voltage Digital Circuit Design: A Comparative Study,” 11th IEEE Faible Tension Faible Consommation (Low Voltage Low Power Conference), June 2012

33. B. A. Alsaify, D. R. Thompson, and J. Di, “Identifying Passive UHF RFID Tags Using Signal Features at Different Tari Durations,” 2012 IEEE International Conference on RFID, April 2012

34. M. Linder, J. Di, and S. C. Smith, “MTD3L – A Secure IC Design Methodology with Reduced Overhead,” 11th International Conference on Microelectronics, Optoelectronics, and Nanoelectronics, March 2012

35. B. Hollosi and J. Di, “Adaptive Voltage Scaling and Parallelism in Delay-Insensitive Asynchronous Circuits for Ultra-Low Power,” 2012 Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2012

36. R. Thian, L. Caley, A. Arthurs, B. Hollosi, and J. Di, “An Automated Design Flow Framework for Delay-Insensitive Asynchronous Circuits,” 2012 IEEE SoutheastCon, March 2012

37. G. Fu, H. Alan Mantooth, and J. Di, “A New Topology for Fully Differential Amplifiers that Enhances Their Tolerance to External Disturbances,” to appear on 2011 IEEE International Conference on ASIC (ASICON 2011)

38. A. Arthurs and J. Di, “Comparative Study of Asynchronous Circuits Designed in Bulk CMOS and FD-SOI for Ultra-Low VDD Operation,” 2011 IEEE Subthreshold Microelectronics Conference

39. A. Arthurs, P. Wyatt, and J. Di, “Modeling SOI MOSFETs under Subthreshold Operation and PV Variation,” 2011 IEEE Subthreshold Microelectronics Conference

40. B. Hollosi, J. Di, S. C. Smith, and H. A. Mantooth, “Delay-Insensitive Asynchronous Circuits for Operating under Extreme Temperatures,” 2011 Government Microcircuit Applications & Critical Technology Conference (GOMACTech)

41. G. Fu, J. Di, and H. A. Mantooth, “A 12-bit CMOS Current Steering D/A Converter with a Fully Differential Voltage Output,” 2011 International Symposium on Quality Electronic Design (ISQED)

42. L. Zhou, S. Smith, and J. Di, “Bit-Wise MTNCL: an Ultra-Low Power Bit-Wise Pipelined Asynchronous Circuit Design Methodology,” 2010 IEEE Midwest Symposium on Circuits and Systems, August 2010

43. S. C. Smith, D. Roclin, and J. Di, “Delay-Insensitive Cell Matrix,” 2010 International Conference on Computer Design, July 2010

44. D. Coleman and J. Di, “Investigation and Design Modification of Delay-Insensitive Asynchronous Circuits for Minimum Supply Voltage Operation,” 2010 IEEE SoutheastCon, March 2010

45. W. Cilio, M. Linder, C. Porter, J. Di, S. C. Smith, and D. R. Thompson, “Side-Channel Attack Mitigation Using Dual-Spacer Dual-Rail Delay-Insensitive Logic (D3L),” 2010 IEEE SoutheastCon, March 2010

46. S. Periaswamy, D. Thompson, H. Romero, and J. Di, “Fingerprinting Radio Frequency Identification Tags using Timing Characteristics,” 2010 Workshop on RFID Security (RFIDsec’10 Asia)

47. B. Hollosi, T. Zhang, R. Nair, Y. Xie, J. Di, and S. Smith, “Investigation and Comparison of Thermal Distribution in Synchronous and Asynchronous 3D ICs,” 3rd International Conference on 3D System Integration (3DIC), September 2009

48. R. Parameswaran, S. Smith, and J. Di, “Delay-Insensitive Ternary Logic,” 2009 International Conference on Computer Design, July 2009

49. A. Alzahrani, A. Bailey, G. Fu, and J. Di, “Glitch-Free Design for Multi-Threshold CMOS NCL Circuits,” 2009 Great Lake Symposium on VLSI, May 2009

50. M. Byers and J. Di, “Low Power Modular Integer Exponentiation using Discrete Logarithm Transformation,” IEEE Microsystems and Nanoelectronics Research Conference, August 2008

51. A. D. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, “Ultra-Low Power Delay-Insensitive Circuit Design,” 2008 IEEE Midwest Symposium on Circuits and Systems, Aug. 2008

52. M. Barlow, G. Fu, B. Hollosi, C. Lee, J. Di, H. A. Mantooth, M. Schupbach, and R. Berger, “A PFET-Access Radiation-Hardened SRAM for Extreme Environments,” 2008 IEEE Midwest Symposium on Circuits and Systems, Aug. 2008

53. B. Hollosi, G. Fu, M. Barlow, C. Lee, J. Di, S. C. Smith, H. A. Mantooth, and M. Schupbach, “Delay-Insensitive Asynchronous ALU for Cryogenic Temperature Environments,” 2008 IEEE Midwest Symposium on Circuits and Systems, Aug. 2008

54. S. Periaswamy, D. Thompson, and J. Di, “Ownership transfer of RFID tags based on electronic fingerprint,” 2008 International Conference on Security and Management (SAM’08), July 2008

55. J. Bourne, R. Schupbach, B. Hollosi, J. Di, A. B. Lostetter, H. A. Mantooth, “Ultra-Wide Temperature (-230°C to 130°C) DC-Motor Drive with SiGe Asynchronous Controller,” 2008 IEEE Aerospace Conference

56. J. Di and S. Smith, "A Hardware Threat Modeling Concept for Trustable Integrated Circuits," IEEE Region 5 Technical Conference, Apr. 2007

57. A. Arthurs and J. Di, "Overflow Detection and Correction in a Fixed-Point Multiplier," IEEE Region 5 Technical Conference, Apr. 2007

58. S. Smith and J. Di, "Detecting Malicious Logic through Structural Checking," IEEE Region 5 Technical Conference, Apr. 2007

59. M. Barlow, V. Varadan, J. Di, and K. Phan, "A Compact, Self-Contained Cough Monitoring System," IEEE Region 5 Technical Conference, Apr. 2007

60. J. Di, "A Framework on Mitigating Single Event Upset using Delay-Insensitive Asynchronous Circuit," IEEE Region 5 Technical Conference, Apr. 2007

61. D. Thompson, J. Di, H. Sunkara, and C. Thompson, "Categorizing RFID Privacy Threats with STRIDE," the 2006 Symposium on Usable Privacy and Security (SOUPS), July 2006, Pittsburgh, PA

62. T. Cao, R. Broughton, J. Penumarthi, J. Di, and H. A. Mantooth, "Analog/digital circuit design in SiGe for space applications," the 4th Annual International Planetary Probe Workshop, June 2006

63. R. Broughton, R. Yelleswarapu, J. Di, and H. A. Mantooth, "Supply voltage scalability comparison of synchronous and asynchronous digital circuits under low temperature to examine suitability for space applications," the 7th International Workshop on Low Temperature Electronics (WOLTE 7), June 2006

64. J. Di and P. K. Lala, "Testability Analysis of Delay-Insensitive Nanoscale Circuits on Cellular Arrays," Invited paper, the 9th World Conference on Integrated Design & Processing Technology, San Diego, CA, June 2006

65. J. Di, P. K. Lala, and D. Vasudevan, "Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays," The 3rd IEEE International Workshop on Electronic Design, Test & Applications (DELTA), 2006

66. C. S. Nam, J. Di, L. W. Borsodi, and W. Mackay, "A Haptic Thermal Interface: Towards Effective Multimodal User Interface Systems," The IASTED International Conference on Human-Computer Interaction (IASTED-HCI 2005), Nov. 2005

67. J. Di and F. Yang, "D3L - A Framework on Fighting against Non-invasive Attacks to Integrated Circuits for Security Applications," the IASTED International Conference on Circuits, Signals, and Systems (CSS 2005).

68. J. Di, P. K. Lala and D. Vasudevan, "On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits," Defect and Fault Tolerance in VLSI Systems Symposium 2005 (DFT 2005), Oct. 2005

69. J. Di and J. S. Yuan, "Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers," The 2005 International Conference on Computer Design (CDES 05).

70. J. Di and J. S. Yuan, "Energy-aware dual-rail bit-wise completion multiplier design," IEEE SoutheastCon 2005, Apr. 05.

71. J. Di and J. S. Yuan, "Run-time Reconfigurable Power-aware Pipelined Signed Array Multiplier Design," International Symposium on Signals, Circuits and Systems, Jun. 2003.

72. J. Di and J. S. Yuan, "Power-aware Pipelined Multiplier Design Based on 2-Dimensional Pipeline Gating," 2003 Great Lake Symposium on VLSI, Apr. 2003.

73. J. Di, J. S. Yuan, and R. Demara, "High Throughput Power-aware FIR Filter Design by Fine-grain Pipelining Multipliers and Adders," IEEE Computer Society Annual Symposium on VLSI, Feb. 2003.

74. J. Di, J. S. Yuan, and M. Hagedorn, "Switching Activity Modeling of Multi-rail Speed-independent Circuits -- A Probabilistic Approach," IEEE 45th Midwest Symposium on Circuits and Systems, Aug. 2002.

75. J. Di, J. S. Yuan, and M. Hagedorn, "Energy-aware Multiplier Design in Multi-rail Encoding Logic," IEEE 45th Midwest Symposium on Circuits and Systems, Aug. 2002.

 

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